Elite winter course on digital ASIC design

TUT, Nokia and Synopsys are organizing a special hands-on course on modern digital ASIC design in periods 2-3 in 2017-2018. The need of ASIC professionals is rapidly increasing in Finland, and passing this course opens excellent job and Master’s thesis opportunities in Nokia in spring 2018.

We search for master and postgraduate students who already know the FPGA and digital design flow. Preferred pre-requisite courses are TIE-50106 Digital design and TIE-50206 Logic Synthesis, or corresponding skills. Compared to FPGA, this course branches towards digital IC backend after the RTL level design, and ends up with an ASIC design (GDSII) ready for fabrication at a chip foundry.

We use the professional Synopsys ASIC tools, current technology libraries (32/90nm) and reference methodology with a hands-on design case. The course includes the following topics:

  • RTL Synthesis to Netlist
  • DFT and ATPG
  • Floorplanning
  • Place and Route
  • Formal Equivalence Checking
  • Timing constraints and STA
  • Chip Finishing (extraction, DRC/LVS)

The course is organized as a Post-Graduate Seminar on Pervasive Computing (TIE-12206 2017-13). Both master’s and postgraduate students are welcome. The course starts in period 2/2017, and includes three intensive lecture sessions, after which there are weekly exercises in a computer class. We will be flexible in times as this is an extra course not regularly scheduled.

Sign up today to TIE-12206 2017-13, but at the latest by October 8 2017, since we can accommodate at most 30 50 students.

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3 Responses to Elite winter course on digital ASIC design

  1. Pingback: New seats for the elite winter ASIC course | TUT Pervasive Computing Blog

  2. Risdiyan says:

    What is the DFT and ATPG?

  3. Eliza Tyas says:

    Thankyou for sharing, maybe It need more info again

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