ORConf 2018 in Gdansk

This year ORConf, the open source digital design conference, was hosted by Gdansk University of Technology in Poland. Three days of presentations and discussion covered an amazing range of topics such as RISC-V, tooling, hardware description languages (HDL), formal verification, licensing, and project updates just to name a few. A full list of the presentation topics can be found on the ORConf webpage and also both the slides and video recordings should be available soon.

Before the conference officially started, I had a few hours time to walk around the Old Town of Gdansk, which is filled with wonderful architecture, cozy restaurants and small shops. Walking is definitely the easiest way to get around since many of the streets are closed for car traffic and the distances between interesting spots are short.

Friday featured talks on RISC-V instruction set architecture, some of its open-source implementations, toolchain and leveraging the Scala programming language for designing hardware. The PULP project has developed a whole RISC-V platform targeting the low energy needs of IoT devices with an array of cores. Another interesting implementation is the SCR1, which provides a full MCU that can be configured for small area and has both academic and commercial users.

Saturday focused more on the open-source tools already available or under development. Projects such as nextpnr (place-and-route) and Symbiflow (bitstream generation) really show the amazing effort dedicated on providing open-source tools for FPGA development. Before lunch we had a rapid-fire of project introductions in the form of 3-minute lightning talks, including a live demo. Perhaps the most anticipated speaker for the day was Wilson Snyder, the main author of the free Verilog HDL simulator Verilator, who presented how adding multithreading speeds up the simulation in the latest version. As for something new in ORConf, we finished the second day with a panel discussion around the topic of the next major step for enabling open-source hardware. This and many other discussions continued late at the traditional conference dinner in the Old Town.

Frank K. Gürkaynak giving his talk on open-source hardware licensing and his experience on the (non-)collaboration of the industrial players.

On the third and final day the topics ranged from system-on-chip debugging to VHDL methodology for verification. Also Haskell was proposed as an HDL enabling the designers to use functional programming techniques for generating Verilog and VHDL. All in all, these three days certainly catered interesting topics for everybody and served as a great forum for discussion on anything related to open-source hardware.

As a final note I wish to thank the organizers at FOSSI foundation for their work to make ORConf possible.

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