Lessons learned from teaching SoC design

Our paper on teaching System-on-Chip design will be presented at the 10th European Workshop on Microelectronics Education (EWME 2014) next week. The article discusses our experiences regarding the teaching practices, especially the mandatory exercise work. Students implement a video encoder on FPGA which teaches e.g. intellectual property (IP) reuse, platform-based design, and HW/SW co-design.

Managing the design complexity is the key, requiring discipline, reuse, and appropriate design tools. Already in a small system like this, the file count is over 400 and line count over 70k. Moreover, SoC designers must master many design styles, languages, and tools.

Various design and debug styles

Various design and debug styles

It has proved good that teachers split the large exercise into mandatory weekly tasks and bonus points are awarded for good work. This balances the workload and helps in estimating the effort. Automated testbenches and startup examples were also very useful. Minor – but manageable ­­– obstacles were encountered with versioning, EDA tool inter-operability, “almost-ready” IP components, and the art of debugging. Nevertheless, students consider the course and hands-on exercises motivating, even if the required time for exercises is 10-80% larger than they estimated (40-80h on average). In the future, more effort is needed in finalizing the reusable IP blocks and whole project works for easier reuse as well as setting up a common repository.


[Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen, Experiences from System-on-Chip design courses, accepted to Tenth Workshop on Microelectronics Education (EWME), Talinn, Estonia, 14-16 May 2014, 6 pages.]

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